A configuration of the data transmission in the prior art will be explained hereunder.
FIG. 16 is a system configurative view showing a system configuration in connection with the data transmission.
In FIG. 16, 100 is a primary board on the data transmission transmitter side, 200 is a secondary board on the data transmission receiver side, and 300 is a data transmission bus for connecting the primary board 100 and the secondary board 200.
In this case, a plurality of secondary board A 200a, secondary board B 200b, . . . , secondary board N 200n as the secondary board 200 are connected to the primary board 100 via the data transmission bus 300.
FIG. 17 is a view showing an internal configuration of the secondary board in the prior art. In FIG. 17, 201 is a trigger signal (TRG) showing write timing/read timing of the data transmission bus 300, 202 is FRAME showing that the data transmission bus 300 is in transfer, 203 is WRL showing that the data transmission bus 300 is in the writing operation, 204 is RDL showing that the data transmission bus 300 is the reading operation, 205 is a signal A1:0 showing lower two bits of the data transmission bus 300, 206 is a multiplex bus A15:2/D15:0 contained in the data transmission bus 300, for sharing address signals and data signals in a time sharing system to show addresses 15 to 2 and data 15 to 0, 207 is a separator for separating the multiplex bus into an address bus and a data bus, 208 is a memory for storing contents of the data transmission, 209 is an address bus MA15:0 for connecting the separator and the memory, 210 is a data bus MD15:0 for connecting the separator and the memory, 211 is a memory writing signal MWRL for connecting the separator and the memory, and 212 is a memory read signal MRDL for connecting the separator and the memory.
FIG. 18 is a flowchart showing an internal process in the separator 207.
In step S201, in order to detect whether or not the data transmission about own board is present, the separator 207 stands by until FRAME 202=L and A15:0=own address are satisfied.
If the present conditions are satisfied in step S201, either WRL=L or RDL=L is detected in step S202 in order to decide whether or not the data transmission is to read or write.
Here, in the case of RDL=L, the process goes to step S203 to show the read (reading process). In the case of WRL=L, the process goes to step S204 to show the write (writing process).
When the reading process (step S203) or the writing process (step S204) is completed, a transmission completing process is carried out and then a series of transmission processes are ended.
-Reading Process-
Next, the reading process (step S203) will be explained with FIG. 19, FIG. 20, and FIG. 21 hereunder.
FIG. 19 is a timing chart showing time-series operations of respective signals in the reading process.
FIG. 20 is a flowchart showing a series of flows in the reading process of the primary board in the prior art.
FIG. 21 is a flowchart showing a series of flows in the reading process of the separator portion of the secondary board in the prior art.
In step S211, at a leading edge of TRG 201 in a T41 period, the primary board assigns FRAME 202 indicating that the data transmission is being carried out to L, assigns RDL indicating the reading transmission to L, assigns lower two bits of the transmission start address to a signal A1:0 (205), and assigns the upper address to the multiplex bus A15:2/D15:0 (206).
In contrast, the secondary board detects the transmission start of own address based on the process in step S201 at the leading edge of TRG 201 in the T41 period.
The primary board executes step S212 in a T42 period and also stops the output to switch the output direction of the multiplex bus A15:2/D15:0 (206), and then switches the transmission direction of the multiplex bus A15:2/D15:0 (206) from the output to the input in step S213.
The present period is used as a transmission direction switching period of the multiplex bus A15:2/D15:0 (206).
The secondary board interprets the transmission direction switching period of the multiplex bus A15:2/D15:0 (206) based on step S231 at a trailing edge of the TRG 201 in the T42 period, and switches the multiplex bus A15:2/D15:0 (206) from the input direction to the output direction and switches the cycle from the address cycle to the data reading cycle.
The secondary board executes step S232 at a leading edge of TRG 201 in a T43 period to check that the transmission is being executed, then executes step S233 to output the address which is constructed by synthesizing the address A15:2/D15:0 (206) assigned from the primary board in the T42 period and A1:0 (205) to MA15:0 (209), and then controls MRDL 212 based on step S234 to execute the memory read.
Then, the data 1 is output to AD15:2/D15:0 based on step S235.
The primary board executes step S214 at a trailing edge of TRG 201 in a T43 period to read the data 1.
Then, the primary board executes step S215 at a leading edge of TRG 201 in a T44 period to switch A1:0 (205), and outputs the next address to the lower address A1:0 (205).
As for the data 2 to 4, operations of the primary board are similar to step S214 and step S215, and operations of the secondary board can be implemented by repeating a series of processes in steps S232 to S235.
The primary board executes step S220 at a trailing edge of TRG 201 in a T46 period to read the data 4, and then outputs FRAME 202=H in step S221 to indicate the end of the data transmission.
The secondary board detects the end of the transmission based on step S232 to end the reading process.
-Writing Process-
Next, the writing process (step S204) will be explained with FIG. 22, FIG. 23, and FIG. 24 hereunder.
FIG. 22 is a timing chart showing time-series operations of respective signals in the writing process.
FIG. 23 is a flowchart showing a series of flows in the writing process of the primary board.
FIG. 24 is a flowchart showing a series of flows in the writing process in the separator portion of the secondary board.
In step S241, at a leading edge of TRG 201 in a T51 period, the primary board assigns FRAME 202 indicating that the transmission is being carried out to L, assigns WRL indicating the writing transmission to L, assigns lower two bits of the transmission start address to an A1:0 (205), and assigns the upper address to the A15:2/D15:0 (206).
Meanwhile, the secondary board detects the transmission start of own address based on the process in step S201 at a trailing edge of TRG 201 in the T51 period.
The primary board executes step S242 in a T52 period to output the write data 1 to A15:2/D15:0 (206).
In contrast, the secondary board executes step S261 at a trailing edge of TRG 201 in the T52 period to check that the transmission is being executed, and goes to step S262. In step S262, the address (A15:0) that is constructed by synthesizing A15:2/D15:0 (206) and A1:0 (205) is output to MA15:0 (209).
Then, the data on the AD15:2/D15:0 is input in step S263, and MWRL 211 is controlled in step S264 to execute the memory write.
The primary board executes step S243 at a leading edge of TRG 201 in a T53 period to switch A1:0 (205), and outputs the next address to the lower address A1:0 (205).
As for the data 2 to 4, operations of the primary board are similar to step S242 and step S243, and operations of the secondary board can be implemented by repeating a series of processes in steps S261 to S264.
The primary board executes step S251 at a leading edge of TRG 201 in a T56 period, and then outputs FRAME 202=H in step S221 to indicate the end of the data transmission.
The secondary board detects the end of the transmission based on step S261 to end the writing process.
In the above data transmission in the prior art, the number of the data in the continuous transmission is decided by the number of lower address signal lines, and also the lower address signal lines must be added in order to accomplish a great deal of continuous transmission, so that the number of signal lines is increased. Therefore, there is the problem that a cost and packaged parts have a tendency to increase.